A rendering engine for three-dimensional computer graphics is becoming programmable and more processor-like in order to deal with complicated and sophisticated shading algorithms. In particular, a pixel shader or a core of the rendering engine is no longer a hardware unit with a predefined graphics functions implemented therein, but the shader is now a processor that has a built-in arithmetic unit provided with an instruction set. The shader is now capable of flexibly realizing additional functions by programming as CPU is.
Pixel operation processing by the pixel shader is extremely high in parallelism in comparison to arithmetic processing by a general-purpose processor. Furthermore, since the pixel shader has some control mechanisms using a multithread method and/or an interleaving method for hiding latency in pipeline processing, the shader can achieve even a higher degree of pseudo parallelism. The greater the degree of the parallelism in a pixel shader, the greater the possibility to perform arithmetic processing on an identical pixel at the same time will be. Thereby, the other arithmetic processes might occur while performing a read-modify-write (RMW) operation on the pixel, possibly failing to provide an expected operation result. To ensure consistency between multiple arithmetic processes on the identical pixel, it is absolutely necessary for the pixel shader to exercise exclusive control over the arithmetic processes.
In order to achieve exclusive control over the pixel operation processes, RMW function is, conventionally, removed from the pixel shader so that a RMW unit separated from the pixel shader can exercise exclusive control over the read and write from/to the frame buffer. Now since the pixel shader does not access the frame buffer, it requires no exclusive control, and therefore the exclusive control has only to be practiced in the RMW unit solely. This facilitates the implementation of the exclusive control.